A significant feature of a semiconductor device, for example, C-MOS semiconductor integrated circuit device resides in a scaling rule stating that when a size of an element configuring the device is miniaturized, an increase in an operating frequency and a reduction in power consumption are achieved. Heretofore, an integration degree per chip (semiconductor chip) and a performance have been improved by miniaturizing the element. However, a slow down tendency emerges in the improvement of the integration degree or the chip performance with a progress in the miniaturization. As reason therefor, a limit in the miniaturization per se, actualization of a delay in a wiring between elements by increasing the operating speed of the element, an increase in power consumption owing to a leakage problem by miniaturizing the element are enumerated.
On the other hand, in a case of constructing an information processing system of a constant scale, there is a limit in a function of capable of integrating elements in a single chip. Therefore, it is indispensable to arrange plural chips and connect chips to each other. Heretofore, a direction of arranging chips is horizontal, and a transmission distance of a signal between chips is a length equal to or larger than one side of the chip. Therefore, even if an operating speed per chip is increased by the miniaturization, time is still taken in transmission between chips, and therefore, an increase in the operating speed of a total of the system is difficult.
A semiconductor device represented by K. Takahashi, et. al., Japanese Journal of Applied Physics, 40, 3032-3037 (2001) is proposed to deal with the slow down in the improvement of the chip performance or an improvement in the performance of a total system. FIG. 1A shows an outline thereof. FIG. 1A is an outline sectional view showing an example of a semiconductor device chips stacked. K. Takahashi, et. al., Japanese Journal of Applied Physics, 40, 3032-3037 (2001) discloses a technology in which other semiconductor chips are three-dimensionally stacked on upper and lower sides of a semiconductor chip 100, and information and power are transmitted by a through silicon via (TSV) connecting the chips TSV. It can be expected that a delay in a wiring between elements in a chip and a delay in transmission between the chips which becomes a bottleneck of a total of the system can considerably be reduced, by conducting transmission at a long distance wiring of a signal in the chip and a signal wiring between the chips by a TSV directly above the chip. Incidentally, notation 101 designates a conductor through a silicon substrate (TSV conductor), notation 102 designates a pad, notation 103 designates an insulating layer, notation 104 designates a pillar, notation 105 designates a bump, and notation 110 designates the silicon (Si) substrate.
FIG. 1B is a detailed sectional view of the chip configuring the semiconductor device shown in FIG. 1A. A TSV 130 used here is constructed, by a structure of literally penetrating a silicon substrate and a back face of the substrate by the TSV conductor 101. The TSV conductor 101 is brought into contact with the pad 102 by being received by a wiring layer (wiring in chip) 106 at a circuit face of the chip which is formed with MOSFET 120 or the like including a drain area 111, a source area 112, and a gate electrode 113. The pad 102 and the TSV conductor 101 are brought into contact with other chip via the pillar 104 and the bump 105 configured by tin or the like. The insulating layer 103 is formed and insulation is maintained at portions where the conductors and a silicon (Si) substrate 107 of the chip are brought into contact.
In a case of arranging the TSV in the chip, a circuit element cannot be placed not only at an area of the TSV conductor but at a surrounding thereof. The area is referred to as Keep Out Zone (KOZ). There are two reasons of necessitating the keep out zone. The first reason is derived from a patterning accuracy in forming a TSV. FIG. 2A illustrates views for explaining a relationship between the TSV and KOZ in a chip configuring a semiconductor device staked with chips, an upper view thereof is a sectional view, and a lower view thereof is a plane view of an essential portion. As shown in FIG. 2A, a wiring layer (wiring in chip) 206 connected with a pillar 204 and is formed, to be larger than a diameter of the TSV conductor 101 of the TSV. When a position of the via formed at the silicon substrate is actually deviated from a design value, also an end portion of the TSV conductor 101 is similarly deviated. Unless KOZ is defined as an area of prohibiting to arrange a circuit element here, the circuit element and the TSV conductor 101 are brought into contact, and the circuit is erroneously operated. An accuracy thereof depends on an exposure step technology. Ordinarily, the accuracy is in an order of several μm in contact exposure, and several 100 nm in stepper exposure.
The second reason is that a property of a circuit element arranged at a periphery of a TSV is changed by a stress of the TSV conductor effected on an Si substrate. Copper is ordinarily used as a material of configuring the TSV conductor 101. Thermal expansion coefficients of the copper and silicon that is a material of a substrate differ from each other. Therefore, a stress is generated at the periphery of the TSV after an elapse of a heating step after forming the TSV. A drain current or a threshold voltage is changed by an influence of presence or absence of a stress at a substrate configuring FET 220. Incidentally, notation 220 includes MOSFET or MISFET. An isolation distance from the conductor owing to the second reason ranges from several μm to about 10 μm although depending on an allowable variation width. FIG. 2B illustrates views for explaining a relationship between a TSV and KOZ in a chip configuring other semiconductor device stacked with chips, an upper view thereof is a sectional view, and a lower view thereof is a plane view of an essential portion. As shown in FIG. 2B, even when an exposure step technology is progressed, and the wiring 206 can sufficiently be downsized, FET 220 cannot be arranged in KOZ owing to an influence of stress. Researches on the influence are described in details in Geert Van der Plas, et. al., IEEE Journal of Solid State Circuit, 46, 1, 293-307 (2011), and Samsung, IITC 2011. Incidentally, notation 202 designates a pad.
On the other hand, from a view point of arranging a circuit, when there is an area in which a circuit cannot be configured as in a TSV or KOZ, although the circuit can be arranged at an individual transistor level, the circuit may not be arranged at a level of a circuit configured by plural transistors of a comparator or a logical circuit. The portion at which the circuit cannot be arranged becomes a dead space as it is. A size of the dead space depends on a minimum dimension of a circuit used, and is around 1 μm in an ordinary technology.
It is necessary to take the area of KOZ and the dead space at which a circuit element cannot be arranged at a periphery of the via into consideration in designing to arrange the TSV from the reason described above.
A location of arranging a TSV is significantly dependent upon a stacking architecture. In this example, an explanation will be given of the location by classifying the stacking architecture into low density mounting and high density mounting in accordance with a mounting density of a TSV. FIG. 3A is a conceptual view in a case where a TSV is mounted at a low density (TSV is arranged in an IO circuit) in a semiconductor device mounted with a chip, and FIG. 3B is a conceptual view in a case where a TSV is mounted at a high density (TSV is arranged in a logical cell) in a semiconductor device stacked with chips.
First, a number of pieces of TSVs between chips is assumed to be several 100 pieces through several 1000 pieces in the low density mounting shown in FIG. 3A. In this case, plural IC's are connected between stacked chips by using TSVs instead of connecting the plural IC's by using a wiring on a mounting substrate of a background art. In this case, pins of power sources supplied to chips or input/output pins of an IO circuit connected to outside of IC are mainly connected between stacked chips. A stacked memory is pointed out as such a stacking example. The TSVs are generally placed below or contiguous to input/output pads connected to the IO circuit.
On the other hand, the high density mounting shown in FIG. 3B assumes TSVs exceeding 10000 pieces per chip. In this case, element circuits are connected between the stacked chips by using TSVs instead of connecting the element circuits in the same chip by wirings in the chip. Here, the element circuit receives a signal from an IO circuit, and is a portion which is not directly connected to outside of IC. The element circuit is referred to as a core circuit in the meaning of differentiating from the IO circuit. In this case, power sources of element circuit levels of core circuits or inputs/outputs of element circuits are mainly connected between the stacked chips. In such examples of stacked chips, three-dimensional FPGA which arranges and wires logical tiles of FPGA (Field Programmable Gate Array) in three-dimensional directions, and connection of a microprocessor (CPU) and a memory by a wiring having a large bus width are enumerated. The TSV is arranged not by interposing an IO circuit but between element circuits, that is, at an inner portion of a core circuit (for example, refer to Japanese Unexamined Patent Application Publication No. 2010-016377).
A TSV can be classified to that in a case of being arranged at an IO circuit and that in a case of being arranged at a core circuit in view of the stacking examples. FIG. 4 shows a typical layout of a semiconductor chip. A core circuit 401 is laid out at a center, and an IO circuit 402 is arranged at a surrounding thereof in consideration of a number of pins connected to the semiconductor chip, and a number of inputs and outputs. Incidentally, notation 403 designates a pad. The following problem is posed in consideration of KOZ of a TSV in respective cases.